Multiple channel data communication system

ABSTRACT

A multiple channel communications system and method for communication among multiple channels using a channel selectable MODEM. The system is comprised of a coaxial cable, a variety of interface units with attached communicating devices and a channel bridge. The interface units include a MODEM and a microprocessor based support element adapted for the attached communicating device. The channel bridge includes two or more .[.MODEM&#39;s.]. .Iadd.MODEMs .Iaddend.and a microprocessor based computer for receiving data from one MODEM and transmitting the data on another MODEM.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to data communication systems and moreparticularly to a data communication system for broadband coaxial cablewhich supports a plurality of communication channels.

2. Description of the Prior Art

Data communication is the transfer of digital information from one pointto another, usually between a user terminal and a computer. In moresophisticated systems communication may take place between twocomputers, a computer and a remote printer or between combinations ofcomputers, memory devices, terminals, or microprocessors used to controlvarious devices, e.g. burglar alarms, to traffic controls, industrialoperations, etc. Data is transmitted through a communication channel bya transceiver, sometimes referred to as a MODEM. Generally, the channelcomposes a pair of wires but can also assume other forms, e.g. radiofrequency channels, microwave transmission channels, or optical fibers.In many applications a channel has a device at each end such as acomputer connected to a terminal by a pair of wires. Data communicationis also possible where there are more than two devices communicating ona channel.

When more than two using devices are connected to a single communicationchannel there are two methods of data communication. The first method isto assign time slots to the using devices connected to the channel. Ausing device may then transmit data during its time slot and must waituntil the next cycle to transmit again. This method is known as "timedivision multiple access." The second method of communication allows anyusing device to transmit data when the communication channel is notbeing used by another device. This method of communication is referredto as "carrier sense multiple access (CSMA)."

A problem encountered with CSMA communication systems is that datacollision occurs when two devices begin to transmit data at the sametime. A signal sent by one transceiver will reach another transceiver ashort time later, thus during the interim a second transceiver may begintransmitting a signal. The two signals will collide causing the data tobe garbled.

Several methods have been developed for collision detection. One method,described in U.S. Pat. No. 4,063,220, granted to Metcalfe, et al., is tocompare concurrently the cable contents bit by bit against the locallytransmitted contents. If a difference is detected the transmission isaborted. Another method uses a looped cable where a signal istransmitted on an inbound cable and received on an outbound cable. Atransceiver will receive its own transmission after the propagationdelay of the cable. Once the entire transmission is received it is thencompared to the transmitted signal to determine if the data has collidedwith another transmission. This method is inefficient in that acollision is not detected until .[.th.]. .Iadd.the .Iaddend.entiretransmission is received.

When a collision has been detected by one of the above means thetransceiver stops transmitting and backs off before retransmitting thesame data. In order that both transceivers do not restart transmissionat the same time the backoff time is determined either randomly or by apredetermined unique time interval.

In the prior art, data communication systems for coaxial cable have beenlimited to communication on a single channel. A channel is characterizedby its position within the spectrum available (frequency) and the spaceit requires (bandwidth). Baseband coaxial cable has long been used fordata communications. However, due to its physical characteristics onlyone communication channel is practical. Broadband (or CATV) coaxialcable has been used less frequently for data communication although ithas long been used for cable television. The use of broadband coaxialcable for data communication is discussed in the article "BroadbandTechnology Magnifies Local Networking Capability" appearing in DataCommunications, Vol. 9, No. 2, February, 1980. On broadband cable abroader frequency spectrum is available for transmission thus it ispossible to divide the spectrum into frequency bandwidths which can beused for separate channels.

Information is communicated by a MODEM. .[.MODEM's.]. .Iadd.MODEMs.Iaddend.for use on broadband cable must be designed to transmit signalsonly in the frequencies of the channel to which it is assigned.Otherwise, it will cause interference on the other channels. Data isencoded by modulation which is accomplished by a variety of techniques.A problem encountered with modulation is that signals outside thebandwidth of the designated channel are generated. Therefore, it hasbeen necessary to use filters. Filters add greatly to the expense of atransceiver and limit the transceivers operation to a designatedchannel. Thus, in the prior art, .[.MODEM's.]. .Iadd.MODEMs .Iaddend.fordata communication over coaxial cable have been limited to operation ona single communication channel.

SUMMARY OF THE PRESENT INVENTION

It is therefore an object of the present invention to provide a datacommunication system with increased data communication capacity throughuse of multiple communication channels on a broadband coaxial cable.

It is a further object to provide a data communication system modemwhich is inexpensive and capable of programmable channel selection.

It is a further object to provide a data communication system with thecapability of communication between communication channels on a cable.

It is a further object to provide a data communication system cable ofoperating on existing CATV coaxial cable installations.

It is a further .[.objective.]. .Iadd.object .Iaddend.to provide a datacommunication system with improved collision detection.

Briefly, in the preferred embodiment, a data communication system of thepresent invention includes a broadband coaxial cable which serves as thecommunication medium. Connected to the cable are a plurality of.[.MODEM's.]. .Iadd.MODEMs .Iaddend.which are channel selectable.Connected to the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.are interfaces forcontrolling access to the cable and .[.supply.]. .Iadd.for supplying.Iaddend.data to and .[.receive.]. .Iadd.for receiving .Iaddend.datafrom a using device. Also included is a bridge between channels wherebya transmission on one channel may be rebroadcast on another channel.

An advantage of the data communication system of the present inventionis that the data communication capacity for broadband coaxial cable isincreased through the use of multiple communication channels.

Another advantage is that the MODEM may be produced at low cost and iscapable of programmable channel selection.

A further advantage is the capability to communicate data betweencommunication channels on a cable.

A further advantage is that the data communication system of the presentinvention may be installed on existing CATV coaxial cable networksthereby reducing the cost of installing a system.

A further advantage is that improved collision detection is provided.

These and other objects and advantages will no doubt become apparent tothose skilled in the art after having read the following detaileddescription of the preferred embodiment which is illustrated in theseveral figures of the drawings.

IN THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a data communicationsystem of the present invention;

FIG. 2 (comprising two sheets marked 2A and 2B) is a block diagram of anembodiment of a MODEM of the system of FIG. 1;

FIGS. 3(A-E) are waveform diagrams illustrating various input and outputsignals of a data decoder of the MODEM of FIG. 2;

FIG. 4 is a block diagram of the .[.multiplex.]. terminal supportelement of the system of FIG. 1;

FIG. 5 is a block diagram of the multiplex terminal support element ofthe system of FIG. 1;

FIG. 6 is a block diagram of the host support element of the system ofFIG. 1;

FIG. 7 is a block diagram of the channel bridge of the system of FIG. 1;

FIG. 8 is a diagram illustrating the contents and format of a data framein accordance with the present invention; and

FIG. 8(A-C) illustrate the contents of various fields of the data frameof FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is illustrated a block diagram of a datacommunication system in accordance with the present invention andreferred to by the general reference numeral 10. The data communicationsystem 10 includes a central retransmission facility 12 connected at thehead-end of a mid-split or sub-split broadband coaxial cable 14. Thecentral retransmission facility 12 is a standard product availablecommercially such as manufactured by American Modem. The coaxial cable14 is split by a plurality of unidirectional taps 16. The unidirectionaltaps 16 are a standard product in the cable television industry. Thetaps 16 are adapted to block transmission from a device connected to thetap of a signal in the receive frequency bandwidth of the system 10.

The data communication system 10 further includes a channel bridge 18.The channel bridge 18 is connected to the cable 14 at one of theunidirectional taps 16.

The data communication system 10 also includes a terminal interface 20.The terminal interface 20 includes a MODEM 22 and a terminal supportelement 24 connected to the associated MODEM 22. The terminal interface20 is connected to the coaxial cable 14 between the MODEM 22 and anotherof the unidirectional taps 16. The terminal interface 20 is connected toa user terminal 26 at the terminal support element 24.

The data communication system 10 also includes a multiplex terminalinterface 28. The multiplex terminal interface 28 includes another ofthe .[.MODEM.]. .Iadd.MODEMs .Iaddend.22 and a multiplex terminalsupport element 30 connected to the associated MODEM 22. The multiplexterminal interface 28 is connected to the cable 14 between the MODEM 22and another of the unidirectional taps 16. The multiplex terminalinterface 28 is connected to a plurality of user terminals 32 at themultiplex terminal support element 30.

The data communication system 10 also includes a host computer interface34. The host computer interface 34 includes another of the .[.MODEM's.]..Iadd.MODEMs .Iaddend.22 and a host support element 36 connected to theassociated MODEM 22. The host computer interface 34 is connected to thecable 14 between the MODEM 22 and another of the unidirectional taps 16.The host computer interface 34 is connected to a host computer 38 at thehost support element 36.

FIG. 2 is a block diagram of the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22.The .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22 of FIG. 1, all of which areidentical, includes a temperature compensated 10.24 MHz oscillator 40.The output of the oscillator 40 is fed to an amplifier 42. The output ofthe amplifier 42 is fed to a divider 44. The divider 44 divides theinput frequency by two, thus providing a 5.12 MHz output. The output ofthe divider 44 is fed to a multiplier 46. The multiplier 46 multipliesthe input frequency by five, thus providing a 25.6 MHz output.

The output of the multiplier 46 is fed to a main phase lock loop circuit48. The multiplier 46 output is connected to a frequency divider 50,which is tied to a phase comparator 51. The comparator .[.5.]. .Iadd.51.Iaddend.is also tied to a programmable divider 52. The divider 50divides the input signal from the multiplier 46 by a factor of 1024,thus providing a fixed 25 KHz output. The programmable divider 52 haseight channel select inputs which are provided by the terminal supportelement 24, the multiplex terminal support element 30 or the hostsupport element 36. The binary value of the channel select inputdetermines the divisor of the programmable divider 52. The input.[.of.]. .Iadd.to .Iaddend.the programmable divider 52 is provided bythe feedback loop of the main phase lock loop circuit 48 furtherhereafter described. The outputs of the divider 50 and the programmabledivider 52 are fed to the phase comparator 51. In manufacture, the fixeddivider 50, programmable divider 52 and comparator 51 may all be part ofa common semiconductor circuit chip.

The feedback loop of the main phase lock loop circuit 48 includes avoltage controlled oscillator 58, a buffer amplifier 60, a divider 62and a mixer 64. An output of the phase comparator 51 is connected to thevoltage controlled oscillator 58. The output of the voltage controlledoscillator 58 is fed to the buffer amplifier 60. The output of thebuffer amplifier 60 is fed to the divider 62 which divides the inputsignal by ten. The output of the divider 62 is fed to the mixer 64 whichalso has a 10.24 MHz input signal source from the amplifier 42. Theoutput of the mixer 64 is a signal having a frequency equal to thedifference of the frequencies of the inputs and is fed to theprogrammable divider 52.

The operation of the main phase lock loop circuit 48 is .[.believed tobe.]. as follows. The oscillator 40 provides a fixed frequency input tothe phase lock loop circuit 48. The output of the divider 50 is a fixed25 KHz signal. This signal is compared to the output of the programmabledivider 52 by the phase comparator 51. The voltage controlled oscillator58 produces a signal having a frequency controlled by the voltage of theinput from the comparator 51. When the output frequency of theprogrammable divider 52 varies from 25 KHz the phase comparator 151 willadjust the voltage of the signal fed to the voltage controlledoscillator 58 until the frequency of the output from the programmabledivider 52 is 25 KHz at which point the loop is locked and the output ofthe voltage controlled oscillator 58 is a fixed frequency.

The relationship between the frequency of the output of the voltagecontrolled oscillator 58 and the binary value of the channel selectinput of the programmable divider 52 is represented by the followingequation:

    F.sub.o =N(250×10.sup.3)+(102.4×10.sup.6)

where F_(o) is the output frequency of the voltage controlled oscillator58 and N is the value of channel select input.

The signal from the oscillator 40 is also fed to a transmit phase lockloop circuit 66 connected to the output of the amplifier 42. Thetransmit phase lock loop circuit 66 includes a transmit phase lock loopblock 68, a voltage controlled oscillator 70, a buffer amplifier 72, adivider 74 and a mixer 76. Within the transmit phase lock loop block 68is a divider 78, a divider 80 and a phase comparator 82 which inmanufacture all be part of a common semiconductor circuit chip.

The output of the amplifier 42 is fed to the input of the divider 78which is adapted to divide the input frequency by sixty-four. The outputof the divider 78 is fed to the phase comparator 82. The divider 80receives the feedback signal of the transmit phase lock loop circuit 66.The divider 80 divides the input frequency by eleven and feeds theoutput signal to the phase comparator 82. The output of the phasecomparator 82 is fed to the voltage controlled oscillator 70. Thevoltage controlled oscillator 70 also receives an input from a dataencoder network 84. The output of the voltage controlled oscillator.Iadd.70 .Iaddend.is fed to the buffer amplifier 72, the output of whichis fed to the divider 74. The divider 74 divides the input frequency byfive and its output is fed to the mixer 76. The output of the amplifier42 is also fed to a multiplier 86 adapted to multiply the inputfrequency by two. The output of the multiplier 86 is also fed to themixer 76. The mixer 76 will provide an output signal with a frequencyequal to the difference of the frequencies of the inputs from themultiplier 86 and divider 74.

The data encoder network 84 includes a counter 88, a counter 90, a readonly memory (ROM) 92, an inverter 94, a flip-flop 96, a digital toanalog converter 98, an amplifier 100 and a filter 102. The counter 88is tied to a 2.048 MHz clock input source which is also fed to thecounter 90. The counter 88 has four output lines which represent abinary value that is incremented by one for each clock pulse. When thebinary value of the output from the counter 88 is fifteen the next clockpulse will cause the output to be "0". The counter 90 is adapted toproduce an output pulse every sixteenth clock pulse.

The four outputs of the counter 88 are fed to the read only memory 92.The read only memory 92 is also connected to receive a transmit datainput (TXD) which is provided by the terminal support element 24, themultiplex terminal support element 30 or the host support element 36.The transmit data input provides the digital data which is to be encodedby the data encoder 84 and eventually transmitted by the MODEM 22. Theinputs to the read only memory 92 provide the address to a memorylocation. When a memory location is addressed the contents of thatmemory location will be output from the read only memory 92.

The output of the read only memory 92 is fed to an inverter 94. Thecounter 90 also provides an output pulse to the flip-flop 96 whichprovides an output that changes with each pulse from the counter 90. Theoutput of the flip-flop 96 is fed to the inverter 94. The inverter 94will output the complement of the input from the read only memory 92when the input from the flip-flop 96 is a logical "1" and will notoutput the complement when it is a logical "0".

The output of the inverter 94 is fed to the digital-to-analog converter98. The digital-to-analog converter 98 outputs a voltage which isselected by the digital inputs from the inverter 94. The output of thedigital-to-analog converter is fed to the amplifier 100 the output ofwhich is fed to the filter 102.

The output of the digital to analog converter 98 is an amplitudemodulated signal. The amplitude of a half cycle is selected by thetransmit data input (TXD) to the read only memory 92. If the transmitdata input is a logical "1" then a memory bank is addressed thatproduces outputs that will cause the digital to analog converter 98 toproduce a half cycle signal having an amplitude corresponding to alogical "1". A transmit data input of logical "0" will address a memorybank corresponding to logical "0". The inverter 94 causes every otherhalf cycle from the digital-to-analog converter 98 to be inverted. Thus,the digital transmit data input (TXD) into the data encoder 84 isconverted to an amplitude modulated signal with two bits of data percycle. The output of the flip-flop 96 provides a transmit clock and isfed to the terminal support element 24, the multiplex terminal supportelement 30 or the host support element 36. The transmit clock tells thesupport element 24, 30 or 36 when to output the next bit of data.

The amplitude modulated signal from the data encoder network 84 is fedto the voltage controlled oscillator 70 of the transmit phase lock loopcircuit 66. The output of the voltage controlled oscillator 70 thus willbe a frequency modulated signal with a center frequency generated by thetransmit phase lock loop circuit 66. The center frequency generated bythe transmit phase lock loop circuit 66 is 111.2 MHz.

The output signal from the transmit phase lock loop circuit 66 is fed toan amplifier 104. The output of the amplifier 104 is fed to a mixer 106.The output of the main phase lock loop circuit 48 from the voltagecontrolled oscillator 58 is fed to an amplifier 108. The output of theamplifier 108 is also fed to the mixer 106. The mixer 106 produces anoutput signal having a frequency equal to the difference of thefrequencies of the inputs. Thus, the transmit frequency at the output ofthe mixer 106 will be a function of the channel select input of theprogrammable divider 52.

The output of the mixer 106 is fed to an amplifier 110. The output ofthe amplifier 110 is fed to a second amplifier 112. The second amplifier112 also receives an input from a power control circuit 114. The outputof the amplifier 112 is fed to a power amplifier 116 the output of whichis then fed to a transmit mute 118.

An integrator 120 has an input connected to the phase comparator 51 anda request to send input from the terminal support element 24, themultiplex terminal support element 30 or the host support element 36.The output of the integrator 120 is fed to a mute 122. The output of themute 122 is fed to a mute drive 124 the output of which is fed to thetransmit mute 118. When the main phase lock loop circuit 48 is not in alocked state the phase comparator 51 will provide an output to theintegrator 120. The main phase lock loop circuit 48 would be in anunlocked state for a brief period after the channel select input ischanged. When this condition exists the integrator 120 will provide asignal to the mute 122 which will cause the transmit mute 118 to preventthe MODEM 22 from transmitting a signal. When data is ready to betransmitted the terminal support element 24, multiplex terminal supportelement 30 or the host support element 36 will send a request to send(RTS) signal to the integrator 120. When the integrator 120 receives arequest to send a signal it will provide an output to the mute 122 whichwill cause the transmit mute 118 to allow the signal from the poweramplifier 116 to be fed to a filter 126. The output of the filter 126 isfed to the cable 14. Thus, the MODEM 22 will transmit a signal only whenthe main phase lock loop circuit 48 is locked and a request to sendsignal is received from the terminal support element 24, the multiplexterminal support element 30 or the host support element 36.

The MODEM 22 may also receive a signal from the cable 14 which is fed toa filter 128. The output of the filter 128 is fed to a mixer 130 whichalso receives an input from the main phase lock loop circuit 48 which isamplified by the amplifier 108. The output signal from the mixer 130 hasa frequency equal to the difference of the frequencies of the inputs andis fed to a filter 132. The output of the filter 132 is fed to a mixer134 which also receives an input from a 28.15 MHz oscillator 136. Theoutput signal from the mixer 134 has a frequency equal to the differenceof the frequencies of the inputs and is fed to a filter 138. The outputof the filter 138 is fed to a 16.9 MHz IF amplifier 140. An output ofthe IF amplifier 140 is fed to a mute amplifier 142. Thus, when a signal.[.of.]. .Iadd.on .Iaddend.the cable 14 is received by the MODEM 22, themute amplifier 142 will output a carrier detect (CD) signal. The carrierdetect signal is fed to the terminal support element 24, the.[.terminal.]. multiplex .Iadd.terminal .Iaddend.support element 30 orthe host support element 36.

The output of the IF amplifier 140 is an amplitude modulated signalwhich is fed to a data decoder network 144. The data decoder 144includes a precision rectifier 146. The precision rectifier 146 invertsthe lower half of each cycle of the input. The output of the precisionrectifier 146 is fed to a zero cross detector 148 which also has a zeroreference input V₀ connected through a resistive element 150. When theinput to the zero cross detector 148 from the precision rectifier 146 iszero volts the zero cross detector 148 will produce an output pulse. Theoutput of the precision rectifier 146 is also fed to a one detector 152which also receives a reference input V₁ connected through a resistiveelement 154. When the input to the one detector 152 from the precisionrectifier 146 reaches the level corresponding to a logical "1" the onedetector 152 will produce an output pulse. The level of a half cyclecorresponding to a logical "0" is lower than the level corresponding toa logical "1". Thus, when a half cycle carries a "0" bit the onedetector will not produce an output pulse.

The output of the zero cross detector 148 is fed to a counter 156. Thecounter 156 receives a 2.048 MHz clock input. The clock frequency issixteen times the data rate. The counter 156 is reset to zero each timea zero cross is detected by the zero cross detector 148. The counter 156will produce an output pulse when the count reaches eight. The counter156 will then remain in an inactive state until it receives a resetpulse from the zero cross detector 148. A latch 158 receives inputs fromthe one detector 152 and the counter 156. When the latch .Iadd.158.Iaddend.receives a pulse from the counter 156 it will output thevoltage present at the input from the one detector 152. The counter 156outputs a pulse at the peak of a half cycle of the input to the datadecoder 144. Thus, the latch 158 outputs the received data in a digitalform.

The data decoder network 144 also provides a receive clock output(RXCLK). The counter 156 sends a pulse to a counter 160 which alsoreceives an input from the 2.048 MHz clock. The input pulse to thecounter 160 from the counter 156 resets the counter 160. The counter 160will produce an output pulse some number of clock pulses later. Thereceive clock output (RXCLK) and the receive data output (RXD) of thedata decoder 144 are fed to the terminal support element 24, themultiplex terminal support element 30 or the host support element 36.When the support element 24, 30 or 36 receives a pulse from the receiveclock output it will read the receive data output (RXD). Thus, thenumber of clock pulses from the 2.048 MHz clock that will cause thecounter 160 to output a pulse should be less than sixteen so that theoutput of the latch 158 is read by the terminal support element 24, themultiplex support element 30 or the host support element 36 before thenext bit of data is output from the latch 158.

In FIG. 3 there is illustrated waveforms for various input and outputsignals of the data decoder network 144 of the MODEM 22. FIG. 3(A)illustrates an input signal to the data decoder 144 carrying the fourbit code of 1001. Each cycle of the signal contains two bits of datawhere each bit is represented by the amplitude of a half cycle. FIG.3(B) illustrates the waveform of the output signal from the precisionrectifier 146. It may be noted that the lower half cycle of the input tothe precision rectifier 146 is inverted. The output from the zero crossdetector 148 is illustrated in FIG. 3(C). FIG. 3(D) illustrates theoutput from the one detector 152 and FIG. 3(E) illustrates the outputfrom the latch 158.

FIG. 4 is a block diagram of the terminal support element 24 of FIG. 1and further illustrating the interface of MODEM 22 and the terminal 26.The terminal support element 24 includes a central processor unit (CPU)162 connected to data and address buses 164. The terminal supportelement 24 also includes a memory block 165 including a random accessmemory chip (RAM) 166, a programmable read only memory chip (PROM) 168,a read only memory chip (ROM) 170, and an erasable programmable readonly memory chip (EPROM) 172. Each chip of the memory block 165 isconnected to the data and address buses 164.

The terminal support element 24 also includes an input/output block 174which includes a support device 176, a universal synchronousreceiver/transmitter (USRT) 178, a universal asynchronousreceiver/transmitter (UART) 180 and a data encryption/decryption device(CRYPTO) 182. Each chip of the input/output block 174 is connected tothe data and address buses 164.

The data and address buses 164 are also connected to a control chip 184.The support device 176 is connected by a plurality of lines to a latch186. The control chip 184 is connected from several device selectoutputs to each of the chips in the input/output block 174 and to thelatch 186. The control chip 184 receives three address lines which aredecoded by the control chip 184. The control chip 184 will then providean output on one of the device select lines to the appropriate chipcorresponding .Iadd.to .Iaddend.the address.[.<.].received.

Each of the chips in the input/output block 174 has an interrupt requestoutput (IRQ). The IRQ output of the support device 176 is connected tothe I/O port line P0 of the support device 176 and to one input of anopen collector AND gate 168. The IRQ output of the .[.ADLC.]. .Iadd.USRT.Iaddend.178.[.<.].is connected to the I/O port line P1 of the supportdevice 176 and to one input of the AND gate 188. The IRQ output of theUART 180 is connected to the I/O port line P2 of the support device 176and.[.<.].to one input of an open collector AND gate 190. The IRQ outputof the CRYPTO 182 is connected to the I/O port line P3 of the supportdevice 176 and to one input of the AND gate 190. The outputs of the ANDgates 188 and 190 are connected at a terminal 192. The terminal 192 isconnected to the IRQ input of the CPU 162.

When one of the chips in the input/output block 174 requires servicingby the CPU 162 the chip will generate an interrupt request. The IRQoutput is normally high and when an interrupt request is generated theIRQ output goes low. Thus, when no interrupt requests are outstandingthe inputs to the AND gates 188 and 190 are high and the outputs of theAND gates 188 and 190 are high. When an interrupt request is generatedan input to the AND gate 188 or 190 will go low causing the output ofthe other AND gate 188 or 190 to be drawn low. This result is achievedbecause the AND gates 188 and 190 are open collector-type AND gates.When the interrupt request is received by the CPU 162 it will read astatus register of the support device 176. The status register of thesupport device 162 is set by the I/O port line P0, P1, P2 or P3 toindicate the source of the interrupt request. The CPU 162 will thenservice the appropriate chip of the input/output block 174.

The CPU 162 has a RESET output. The RESET output is connected to thedevices in the input/output block 174 and to the latch 186. When thepower to the terminal support element 24 is turned on the CPU 162 willgenerate an output on the RESET line. The devices receiving the RESETsignal are set to initial conditions.

The CPU 162 has a clock synchronization output labeled E. The E outputof the CPU 162 is connected to the RAM 166, the ROM 170, the supportdevice 176, the .[.ADLC.]. .Iadd.USRT .Iaddend.178, the CRYPTO 182 andthe control chip 184. The clock synchronization output E from the CPU162 provides a clock signal to the connected devices. The CPU 162 has anoutput labeled R/W connected to the RAM 166, the ROM 170, the supportdevice 176, the USRT 178, the UART 180 and the CRYPTO 182. The R/Woutput of the CPU 162 indicates to the connected devices whether the CPU162 is in a read or write state.

The latch 186 has eight output lines connected to the channel selectinputs of the MODEM 22. The carrier detect output (CD) from the MODEM 22is connected to the support device 176. The ADLC 178 has a TXD outputconnected to the MODEM 22. The USRT 178 receives TXCLK, RXD and RXCLKinputs from the MODEM 22. The RTS output from the USRT 178 is connectedto the MODEM 22.

An EIA converter 194 is connected to the UART 180 by a plurality oflines 195 which carry the necessary signals for the terminal 26. The EIAconverter 194 is connected to the terminal 26 by a plurality of lines196. The EIA converter 194 transforms the signals passing between theUSART 180 and the terminal 26 to the appropriate level.

The CRYPTO 182 is an optinal feature of the terminal support element 24.The CRYPTO 182 provides for encryption and decryption of the datatransmitted over the cable 14. The PROM 168 provides the "key" for theencryption and decryption. A receiving support element 24, 30 or 36 musthave the same "key" as the transmitting support element 24, 30 or 36.

The RAM 166 provides for extended data buffering to increase thecapability of the data communication system 10. The EPROM 172 allows forthe addition of special features to the data communication system 10.

FIG. 5 is a block diagram of the multiplex terminal support element 30and also shows the connection to the MODEM 22 and to the terminals 32.The architecture of the multiplex terminal support element 30 is similarto that of the terminal support element 24. The encryption/decryptionfeature illustrated in FIG. 4 has been omitted and also the EPROM 172for provision of special features is not shown. These features may beincluded in the multiplex terminal support element 30 but are omitted tosimplify the description. The CRYPTO .[.174.]. .Iadd.182 .Iaddend.andPROM 168 would be necessary in the multiplex terminal support element 30if encrypted data is to be received or transmitted.

The multiplex terminal support element 30 includes a CPU 197 .[.is.].connected to a data .[.bus.]. and address bus 198. A RAM 200 isconnected to the data and address buses 198. The RAM 200 includesapproximately two thousand bytes of memory. A ROM 202 is also connectedto the data and address buses 198. The ROM 202 includes approximatelyfour thousand bytes of memory. Also connected to the data and addressbuses 198 are a support device 204, a USRT 206, eight .[.UART's.]..Iadd.UARTs .Iaddend.208 and a control 210. The support device 204 isconnected to a latch 212 by eight parallel lines. The latch 212 isconnected to the channel select input of the MODEM 22 by eight parallellines. The support device 204 receives a carrier detect input from theMODEM 22. The USRT 206 is connected to the MODEM 22. Each of the eight.[.UART's.]. .Iadd.UARTs .Iaddend.208 is connected to an EIA converter214 and each of the eight EIA converters 214 is connected to one of theeight terminals 32.

The multiplex terminal support element 30 requires a larger block ofrandom access memory than the terminal support element 24. The multiplexterminal support element 30 also includes eight .[.UART's.]. .Iadd.UARTS.Iaddend.208 where the terminal support element 24 includes only oneUART 180. The eight .[.UART's.]. .Iadd.UARTS .Iaddend.208 are necessaryto enable the multiplex terminal support element 30 to be connected tothe eight terminals 32. The read/write, clock synchronization reset andinterrupt request signal are connected to and from the CPU 197 in thesame manner as with the CPU 162 of the terminal support element 24. Thedevice select outputs from the control 210 are connected in the samemanner as for the control 184 of the terminal support element 24, theonly difference being that additional device select outputs arenecessary from the control 210 to connect to the additional .[.UART's.]..Iadd.UARTs .Iaddend.208.

FIG. 6 is a block diagram of the host support element 36 of FIG. 1 andalso shows the connection to the MODEM 22 and to the host computer 38.The architecture of the host support element 36 is similar to that ofthe terminal support element 24 and the multiplex terminal supportelement 30. Again the encryption/decryption feature .Iadd.of CRYPTO 182.Iaddend.and the EPROM 172 have been omitted for simplification.

The host support element 36 includes a CPU 216. The CPU 216 is connectedto a data .[.bus.]. and address bus 218. A RAM 220 is connected to thedata and address .[.buses.]. .Iadd.bus .Iaddend.218. The RAM includesapproximately two thousand bytes of memory. A ROM 222 is also connectedto the data and address buses 218. The ROM 222 includes approximatelyfour thousand bytes of memory. Also connected to the data and addressbuses 218 are a support device 224, a USRT 226, a direct memory accesscontroller (DMAC) 228, a host interface 230 and a control 232. Thesupport device 224 is connected to a latch 234 by eight parallel lines.The latch 234 is connected to the channel select input of the MODEM 22by eight parallel lines. The support device 224 receives a carrierdetect input from the MODEM 22. The USRT 226 is connected to the MODEM22. The host interface 230 is connected to the host computer 38.

The host interface 230 comprises a circuit supplied by the manufacturerof the host computer 38. The host interface 230 will interface thesignals from the host computer 38 to the host support element 36. TheDMAC 228 transfers data directly between the RAM 220 and the hostinterface 230. The direct memory access feature is included in the hostsupport element 36 to facilitate the higher speed generally encounteredwith the host computer 38.

FIG. 7 is a block diagram of the channel bridge 18 of FIG. 1. Thechannel bridge 18 includes a CPU 236 connected to a data .[.bus.]. andaddress bus 238. The channel bridge 18 also includes a RAM 240 and a ROM242 each connected to the data and address .[.buses.]. .Iadd.bus.Iaddend.238. Also connected to the data and address bus 238 are asupport device 244, a plurality of .[.USRT's.]. .Iadd.USRTs.Iaddend.246, a DMAC 248, a UART 250 and a control 252. The supportdevice 244 is connected to a plurality of latches 254 by eight parallellines. Each of the latches 254 is connected to the channel select inputof each of the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22. Each of the.[.USRT's.]. .Iadd.USRTS .Iaddend.246 is connected to one of the.[.MODEM's.]. .Iadd.MODEMs .Iaddend.22. Each of the .[.MODEM's.]..Iadd.MODEMs .Iaddend.22 is connected to a signal splitter 256. Thesignal splitter 256 is connected to the coaxial cable 14. The UART 250is connected to an EIA converter 258. The EIA converter 258 has aninput/output terminal 260 to provide programmer access to the channelbridge 18. The control 252 has a separate output connected to each ofthe latches 254.

The channel bridge 18 receives signals on a channel and searches forpackets of data directed to a different channel and then retransmitsthose packets onto the appropriate channel. Each MODEM 22, included inthe channel bridge 18, is set to a different channel, thus the channelbridge 18 is capable of providing a direct bridge between a number ofchannels equal to the number of .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22included in the channel bridge 18. Data received by the MODEM 22 istransferred to the USRT 246. When data is being received by several.[.USRT's.]. .Iadd.USRTs .Iaddend.246 simultaneously the CPU 236 willbecome overburdened and incapable of transferring the data to the RAM240. Thus, the DMAC 248 is used to control the transfer of data from the.[.USRT's.]. .Iadd.USRTs .Iaddend.246 to the RAM 240.

The channel on which the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22 operateis selected by storing the appropriate value for the desired channel inthe support device 244, then the appropriate latch 254 is selected bythe control 252 and the output of the latch 254 is held at the desiredvalue. The channel of each of the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.22may be set by enabling the appropriate latch 254.

In practice the number of channels bridged by the channel bridge 18 islimited by the rate at which received data may be transferred to the RAM240 and back to the USRT 246. Thus, several channel bridges 18 may berequired for the data communication system 10. Where several channelbridges 18 are included in the data communication system 10 a packet ofdata may need to be routed through more than one channel bridge 18.Routing through more than one channel bridge 18 may be handled by meansof a routing table stored in the RAM 240.

FIG. 8 illustrates the data format used by the data communication system10. The terminal interface 20, the multiplex terminal interface 28, orthe host computer interface 34 will transmit a frame of data, referredto by the general reference numeral 300, onto the cable 14. The frame ofdata 300 is comprised of bytes of data. Generally each byte is comprisedof eight bits of data where a bit is a logical "1" or "0". The firstbyte of the frame 300 is a .[.flage.]. .Iadd.flag .Iaddend.302. The flag302 has a fixed value of 01111110 and is used to indicate to a receiverthat a stream of data is following. Following the flag 302 is a datafield 304. Following the data field 304 is a cyclic redundancy checkfield 306. The cyclic redundancy check field 306 is two bytes in lengthand is a value generated by the transmitter for the data field 304. Thereceiver generates a cyclic redundancy check value for the receivedframe 300 and by comparing with the value of the received cyclicredundancy check field 306 the receiver detects transmission errors.Following the cyclic redundancy check field 306 is a flag 308. The flag308 has the same value as the flag 302 and indicates the end of theframe 300.

The data field 304 comprises a datagram referred to by the generalreference numeral 310. The datagram 310 includes a destination nodeaddress 312. The destination node address 312 is the first byte of thedatagram 310 and indicates the node which is to receive the frame 300.In the present preferred embodiment a node is defined to be a point inthe cable 14 where the terminal interface 20, the multiplex terminalinterface 28 or the host computer interface 34 is connected. Each nodeis assigned a unique address.

The datagram 310 also includes a channel number field 314 following thedestination node address 312. The channel number field 314 is one bytein length. The channel number field 314 indicates the channel on whichthe destination node is located. When the destination node's channel isdifferent from the source node's channel the frame 300 is routed throughthe channel bridge 18. The channel on which a node is located isdetermined by the channel select input to the MODEM 22.

Following the channel number field 314 is a transport control field 316.The transport control field 316 is one byte in length. The transportcontrol field 316 is followed by a data field 318.

The data field 318 comprises a packet referred to by a general referencenumeral 320. The first byte of the packet 320 is a port field 322. Theport field 322 is one byte in length and indicates the destinationwithin a node, for example, one of the terminals 32 connected to themultiplex terminal interface 28. A control field 324 follows the portfield 322 and is one byte in length. Following the control field is adata field 326 which can be any length less than 64 bytes.

FIG. 8A illustrates the subfields of the transport control field 316. Aversion field 328 comprises the first two bits of the transport controlfield 316. The version field 328 is used to indicate the format of thedata contained in the packet 320. The third and fourth bits of thetransport control field 316 are not used in the presently preferredembodiment. A hop count field 330 comprises the last four bits of thetransport control field 316. When a packet 320 is transmitted by a nodethe hop count field 330 has an initial value of seven. Each time thepacket 320 is routed through the channel bridge 18 the value of the hopcount field is decremented by one. When the value of the hop count fieldequals zero, the packet 320 is discarded. This prevents indefinitelooping of packets in the data communication network 10 due totransmission errors.

FIG. 8B illustrates the subfields of the control field 324 when thefirst bit of the control field 324 is a "1". When the first bit of thecontrol field 324 is a "1" the packet 320 is a data packet. In a datapacket the data field 326 contains the information being communicated.Following the first bit of the control field .[.316.]. .Iadd.324.Iaddend.in a data packet is a flow control bit 332. The flow controlbit 332 is used to adjust for a possible speed mismatch between thetransmitting node and the receiving node. Following the flow control bit332 in a data packet is a sequence field 334. The sequence field 334 isthree bits in length. Following the sequence field 334 in a data packetis an acknowledgement field 336. The acknowledgement field 336 is threebits in length.

The sequence field 334 is incremented each time a packet is sent, thus,indicating the order of the packets sent and enabling the receiver todisassemble the packets 320 in the correct order. The acknowledgementfield indicates the value of the sequence field 334 for the lastcorrectly received data packet.

When a receiving node runs out of buffer space to store the receiveddata it will discard the received packet 320 and transmit a data packetwith the value of the acknowledgement field 336 set to the value of thesequence field 334 of the previously received packet 320 and will setthe flow control bit 332 to enable flow control. In the flow controlenabled state the transmitting node will delay transmission of the nextpacket 320 by a predetermined time delay.

When the transmission of a packet 320 has not been acknowledged by thereceiving node, then after a predetermined time interval thetransmitting node will retransmit the unacknowledged packet. After fiveretransmission attempts the connection will be aborted.

FIG. 8C illustrates the control field 324 when the first bit is "0". A"0" in the first bit of the control field 324 indicates a controlpacket. A control type field 338 follows the first bit of the controlpacket 324. The control type field .[.324.]. .Iadd.338 .Iaddend.containsa control message for the other node in a connection. The types ofcontrol messages include open connection request, open connectionacknowledged, open connection nonacknowledged, close connection requestand close connection acknowledged.

An open connection request control message signals to another(receiving) node in the data communication system 10 that thetransmitting node requests a connection. An open connection acknowledgedcontrol message is sent by the receiving node to signal the transmittingnode that the receiving node is ready to accept transmitted data. Atthis point a connection is established between the transmitting andreceiving nodes. An open connection nonacknowledged is sent by thereceiving node to signal the transmitting .Iadd.node .Iaddend.that thereceiving node is not ready to receive transmitted data in which case noconnection is established. A close connection request control messagesignals the other node in a connection to close the connection. A closeconnection acknowledged signals the other node in a connection that aclosed connection request was received and thus terminates theconnection.

The operation of the data communication system 10 may now be illustratedby way of describing a communication between the terminal 26 and thehost computer 38. In such a situation, a user will type a request at theterminal 26 to open a connection with the host computer 38. The user atthis time will input the address of the host computer 38. The requestwill be transmitted to the UART 180 of the terminal support element 24.The UART 180 will output an interrupt request signal to the CPU 162. TheCPU 162 will respond to the interrupt request by reading the statusregister of the UART 180 which will tell the CPU 162 to begintransferring the contents of the registers to the RAM 166. After thedata from the terminal 26 has been transferred to the RAM 220 of thehost support element 36, the CPU 162 will then read the contents of theRAM 166 which will contain the open connection request. The CPU 162 willassemble the datagram 310 (illustrated in FIG. 8) with the node andchannel address for the host computer 38, set the version and hot countof the transport control field 316, set the first bit of the controlfield 324 to "0" and set the value of the control type field 338 to thecode for an open connection request control message. The data field 326will contain the address of the terminal interface 20. The assembleddatagram 310 is then transferred to the USRT 178 of the terminal supportelement 24. As the datagram 310 is received by the USRT 178, it willgenerate a cyclic redundancy check value which will be placed in thecyclic redundancy check field 306.

Before the CPU 162 enables the USRT 178 to transfer the data to theMODEM 22, the CPU 162 will read the status register of the supportdevice 176 which will indicate whether or not the carrier detect signalis being generated by the MODEM 22. If the carrier detect signal isbeing output by the MODEM 22, indicating that coaxial cable 14 is beingused, then the CPU 162 will delay enabling the USRT 178 until thecarrier detect signal indicates that cable 14 is free. When the cable 14is free the CPU 162 will enale the USRT 178. The USRT 178 will transmita request to send signal to the MODEM 22. When the MODEM 22 receives therequest to send signal it will disenable the transmit mute 118 thus,allowing an output signal to be broadcast onto the coaxial cable 14. TheUSRT 178 will then begin to serially transmit the frame 300 to the MODEM22.

Each time a transmit clock pulse is received from the MODEM 22 the USRT178 will output a bit of data. The bit of data will be received by thedata encoder 84 of the MODEM 22. The data encoder 84 will encode thedata into an amplitude modulated output. The amplitude modulated outputof the data encoder 84 is received by the voltage controlled oscillator70. The frequency of the output from the voltage controlled oscillator70 is determined by the voltage of the inputs from the phase comparator82 and the data encoder 84. The voltage of the input from the dataencoder 84 will be constantly varying, thus, the output frequency fromthe voltage controlled oscillator 70 will vary according to theamplitude of the input from the data encoder. Thus, the data is encodedinto a frequency modulated signal. The output of the voltage controlledoscillator 70 is mixed with the output of the main phase lock loopcircuit .[.56.]. .Iadd.48 .Iaddend.by the mixer 106, thereby making thetransmit frequency a function of the channel select input. The output ofthe mixer 106 is amplified and then transmitted onto the cable 14. Whenthe entire frame 300 has been output from the URST 178 the request tosend signal will be turned off and the MODEM 22 will cease transmitting.

The signal transmitted by the MODEM 22 will be received by the centralretransmission facility 12. The central retransmission facility 12translates the frequency of the received signal to a mathematicallyrelated higher frequency and rebroadcasts the signal at the higherfrequency. In the preferred embodiment the central retransmissionfacility will rebroadcast the signal at a frequency 156.25 MHz higherthan the frequency of the received signal. The unidirectional taps 16permit only signals in the frequency range of approximately 17.7 to 47.7MHz to be transmitted in the direction towards the centralretransmission facility 12 and only signals in the frequency range ofapproximately 173.95 to 203.95 MHz to be transmitted in the directionaway from the central retransmission facility 12. Thus, a communicationchannel is comprised of a transmit frequency bandwidth in the frequencyrange of approximately 17.7 to 47.7 MHz and a receive frequency range ofapproximately .[.123.95.]. .Iadd.173.95 .Iaddend.to 203.95 MHz.

The signal rebroadcast by the central retransmission facility 12 will bereceived by the MODEM 22 included in the host computer interface 34. Thesignal received by the MODEM 22 will be fed through the mixer 130 withinthe MODEM 22. The mixer 130 will also receive an input from the mainphase lock loop circuit 48. Thus, both the transmit frequency andreceive frequency are jointly stepped when the channel select input tothe main phase lock loop circuit 48 is changed. The output of the mixer130 is eventually fed to the IF amplifier 140. The IF amplifier 140converts the frequency modulated input to an amplitude modulated output.The amplitude modulated output of the IF amplifier 140 is then fed tothe data decoder 144. The data decoder 144 converts the amplitudemodulated input to a serial digital output identical to the frame 300generated by the terminal support element 24. The output of the datadecoder 144 is then fed to the host support element 36.

The data received by the host support element 36 is fed to the USRT 226.The first eight bits of data are the flag 302 which indicates the startof the frame 300. The next two bytes of data are the node field 312 andthe channel field 314 which the USRT 226 internally compares to theaddress of the host support element 36. The same comparison is made byall nodes on the channel. The USRT 178 of the terminal support element24 will receive back the flag 302 if the transmission of the frame 300has not collided with a transmission by another node. If the USRT 178does not receive the flat 302 it will continue the transmission in thenormal manner. However, if the USRT 178 does not receive the flag 302 itis presumed that a data collision has occurred and the USRT 178 willstop transmitting the frame 300. The USRT 178 will then send aninterrupt request signal to the CPU 162. The CPU 162 will respond to theinterrupt request by waiting a random time and then retransmitting theframe 300. The random backoff will assure that the terminal supportelement 24 does not restart transmission at the same time that thetransmission from .[.th.]. .Iadd.the .Iaddend.other node is restarted.

If the node field 312 and the channel field 314 contain the address ofthe host support element 36 then the USRT 226 will send an interruptrequest signal to the CPU 216. The CPU 216 will respond to the interruptrequest by enabling the DMAC 228 which will transfer the incoming datafrom the USRT directly to the RAM 220. As the data is received by theUSRT 226 a cyclic redundancy check value is internally computed. Whenthe final flag 308 is received, the cyclic redundancy check valuecomputed by the USRT 226 is compared to the cyclic redundancy checkvalue contained in the cyclic redundancy check field 306. If atransmission error is detected the USRT 226 will output an interruptrequest to the CPU 216. If no transmission error is detected the CPU 216will read the datagram 310 from the RAM 220.

The CPU 216 will then read the control field 324 which contains the openconnection request control message and the address of the terminalinterface 20. If the host computer 38 has an open port the CPU 216 willassemble an open connection acknowledged data packet. The data field 326of the return packet 320 will contain the address of the host computerinterface 34 plus a port address. All future transmissions by theterminal interface 20 will contain the port address in the port field322. The open connection acknowledged data packet will be transmitted bythe host computer 38 in a manner similar to that described for theterminal interface 20.

When the open connection acknowledged control message is received by theterminal interface 20 a connection is established. Once the connectionis established the terminal 26 and the host computer 38 may transmitinformation back and forth between each other. Each time the terminal 26sends a data packet the sequence field 334 will be incremented and theacknowledgement field 336 will be set to the sequence number of thehighest consecutively numbered data packet received from the hostcomputer 38. Likewise, each time the host computer 38 sends a datapacket the sequence field 334 will be incremented and theacknowledgement field 336 will be set to the sequence number of thehighest consecutively numbered data packet received from the terminal26.

When all communication with the host computer 38 is complete the userwill type a request at the terminal 26 to close the connection. Theterminal support element 20 will transmit the request to the hostsupport element 34. The host support element 34 will send back a closeconnection acknowledgement to the terminal support element 20 which willterminate the connection.

Communication through the channel bridge 18 may be illustrated by thefollowing example. A transmitting node is assigned to Channel A and areceiving node is assigned to Channel B. In order for the transmittingnode to send data to the receiving node the data must be routed throughthe channel bridge 18. The channel bridge 18 includes one MODEM 22 setto Channel A and one MODEM 22 set to Channel B. The MODEM 22 set toChannel A feeds the incoming data to the USRT 246. The USRT 246 will seethe flag 302 and then load the next two bytes into registers and comparethe channel field 314 to the code for Channel A. If the channel field314 contains the address of Channel A the USRT 246 will not send aninterrupt request to the CPU 236 since the data does not need to betransferred to another channel. If the channel field 314 does notcontain the address of Channel A then the USRT 246 will send aninterrupt request to the CPU 236. The CPU 236 will respond to theinterrupt request by enabling the DMAC 248 which will transfer thereceived data from the registers of the USRT 246 to the RAM 240. TheUSRT 246 will perform the cyclic redundancy check and send an interrupt.Iadd.request .Iaddend.to the CPU 236 if a transmission error isdetected.

After the received data has been transferred to the RAM 240.Iadd.,.Iaddend.the CPU 236 will read the channel field 314 containing theaddress for Channel B and then begin transferring the received data tothe USRT 246 which is connected to the MODEM 22 set to Channel B. If noother transmissions are detected on Channel B the request to send signalwill be sent to the MODEM 22 and the data will be transmitted onto thecable 14 on Channel B. The USRT 246 associated with Channel B willperform collision detection for the frame 300 retransmitted onto ChannelB in the same manner as was done with the USRT 178 of the terminalsupport element 24. The receiving node will then detect and receive thedata in the normal manner.

The data communication system 10 provides increased data communicationcapacity through the connection of channels by the channel bridge 18.Low cost of the MODEM 22 is achieved by use of the DAC 98 to produce anamplitude modulated signal which is then used to produce a frequencymodulated signal for transmission thus enabling the use of lessexpensive filters. The programmable channel select feature is madepossible by the use of two phase lock loop circuits. The overall expenseof installing the data communication system 10 is reduced by thecapability for use of existing CATV coaxial cable networks.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artafter having read the above disclosure. Accordingly, it is intended.[.tha.]. .Iadd.that .Iaddend.the appended claims be interpreted ascovering all alterations and modifications as fall within the truespirit and scope of the invention.

What is claimed is:
 1. A data communication system comprising:a coaxialcable; a plurality of .[.MODEM's.]. .Iadd.MODEMs .Iaddend.connected tothe cable including means for selecting the transmit and receive.[.frequency bandwidths.]. .Iadd.frequencies .Iaddend.of each of the.[.MODEM's.]. .Iadd.MODEMs.Iaddend.; means connected to the.[.MODEM's.]. .Iadd.MODEMS .Iaddend.for supplying data to and receivingdata from each of the .[.MODEM's.]. .Iadd.MODEMs.Iaddend.; a centralretransmission facility connected at the head end of the cable.[.whereby.]. .Iadd.such that .Iaddend.a signal transmitted by at leastone of the .[.MODEM's.]. .Iadd.MODEMs .Iaddend.is received by thecentral retransmission facility and translated to the receive frequency.[.bandwidth.]. of the MODEM which transmitted said signal; and achannel bridge connected to the cable including two or more.[.MODEM's.]. .Iadd.MODEMs .Iaddend.each of said .[.MODEM's.]..Iadd.MODEMs .Iaddend.having different .[.transmit frequencybandwidths.]. .Iadd.transmitting frequencies .Iaddend.and different.[.receive frequency bandwidths.]. .Iadd.receiving frequencies than theother of said MODEMs in said channel bridge .Iaddend.and including meansfor transferring .[.a signal.]. .Iadd.signals .Iaddend.received by oneof said MODEM's to another of said .[.MODEM's whereby the MODEM's.]..Iadd.MODEMs in the channel bridge such that the MODEMs.Iaddend.connected to the cable which are transmitting and receiving.[.in.]. .Iadd.at .Iaddend.different .[.frequency bandwidths.]..Iadd.frequencies .Iaddend.may receive signals from and transmit signalsto each other .Iadd.via the channel bridge.Iaddend..
 2. The datacommunication system of claim 1, wherein;the coaxial cable comprises abroadband coaxial cable.
 3. The data communication system of claim 1,wherein.[.;.]..Iadd.:.Iaddend.the means connected to some of the.[.MODEM's.]. .Iadd.MODEMS .Iaddend.for supplying data to and receivingdata from the .[.MODEM's.]. .Iadd.MODEMS .Iaddend.include means forsupplying data to and receiving data from a terminal.
 4. The datacommunication system of claim 1, wherein.[.;.]..Iadd.:.Iaddend.the meansconnected to some of the .[.MODEM's.]. .Iadd.MODEMS .Iaddend.forsupplying data to and receiving data from the .[.MODEM's.]. .Iadd.MODEMS.Iaddend.include means for supplying data to and receiving data from aplurality of terminals.
 5. The data communication system of claim 1,wherein.[.;.]..Iadd.:.Iaddend.the means connected to some of the.[.MODEM's.]. .Iadd.MODEMS .Iaddend.for supplying data to and receivingdata from the .[.MODEM's.]. .Iadd.MODEMS .Iaddend.include means forsupplying data to and receiving data from a host computer.
 6. The datacommunication system of claim 1, wherein.[.;.]..Iadd.:.Iaddend.the.[.MODEM's.]. .Iadd.MODEMS .Iaddend.include means for detecting thepresence of a signal on the cable.
 7. The data communication system ofclaim 1, wherein.[.;.]..Iadd.:.Iaddend.the means connected to the.[.MODEM's.]. .Iadd.MODEMS .Iaddend.for supplying data to and receivingdata from each of the .[.MODEM's.]. .Iadd.MODEMS .Iaddend.includes meansfor comparing a plurality of the first bits of data received to thecorresponding bits of data transmitted by one of the .[.MODEM's.]..Iadd.MODEMS .Iaddend.attempting to transmit a signal whereby datacollisions may be detected.
 8. The data communication system of claim 7,wherein;said means for comparing data are included in a universalsynchronous receiver/transmitter.
 9. The data communication system ofclaim 1, further comprising.[.;.]..Iadd.:.Iaddend.encryption meanscoupled with the means for supplying data to and from the .[.MODEM's.]..Iadd.MODEMS .Iaddend.whereby data transmitted over the cable isencrypted by the transmission source and decrypted by the transmissiondestination.
 10. The data communication sytem of claim 9, wherein;theencryption means includes an interchangeable encryption key.
 11. Thedata communication system of claim 10, wherein;said encryption keycomprises an erasable programmable read only memory.
 12. The datacommunication system of claim 1, wherein.[.;.]..Iadd.:.Iaddend.saidmeans for transferring a signal included in the channel bridgecomprises.Iadd.: .Iaddend.a universal synchronous receiver/transmitterconnected to said .[.MODEM's.]. .Iadd.MODEMS.Iaddend., data and addressbuses connected to each of said universal synchronousreceiver/transmitters, a central processing unit connected to said dataand address buses.Iadd., .Iaddend.and memory connected to said data andaddress buses.
 13. A method of collision detection for datacommunication comprising the steps of:formating digital data by atransmitting node whereby a flag is inserted at the beginning of atransmission frame; broadcasting said transmission frame onto a cable;receiving said transmission frame by a central transmission facility;translating said transmission frame by said central retransmissionfacility to a receive frequency bandwidth; rebroadcasting saidtransmission frame in said receive frequency bandwidth onto said cable;receiving said flag of said transmission frame by said transmittingnode; comparing said flag as received to said flag as transmitted todetect a collision of data; aborting the broadcasting of saidtransmission frame when a collision of data is detected; waiting arandom time after detecting a collision of data; and rebroadcasting saidtransmission frame after waiting a random time.